USA patents
Around 1973 I was involved in the development of a telemetry system for the third stage of the ELDO rocket. A number of sensors delivered an analog signal between 0 and 5 volts. I developed a commutator that received all these signals and connected these one by one to an Analog to Digital converter that produced a series of 8 bit digital numbers (Bytes) that were transmitted to an ground station as a series of bit values. There a so called Bit Synchroniser reproduced the transmitted bit values. At that time the performance of typical Bit Synchronisers was poor when the Signal-To-Noise Ratio was small, resulting in loss of data.
My contribution was an improved bit detector that performed close to the theoretical optimum.
Bit Synchonisers make use of a Voltage Controlled Oschilator (VCO). Our VCO was a new digital freqeuency synthesizer that was controlled by a stable Crystal controlled clock that performed significanly better that the then widely used VCOs based upon resistor-capacitor time bases.
3,823,266 Synchronisation System
In our telemetry system the data stream is a sequence of bits, every 8 bits corresponds to one byte and every N bytes represent the analogue value of one of the N sensors mentioned above.
The data is organised in a frame of N bytes in which the first bit is the begin of the byte value of the first sensor. An extra pattern is added thet enables the detection of the begin of a received frame.
For correct reception the receiver must decode the received data exactly synchronously with the transmitted data.
3,876,982 Code Programming Device
Around 1975 I developed a digital pager using the LOCMOS LSI technology, developed at Philips ELCOMA in Nijmegen, the predecessor of ASML. Each pager had to accept a unique binary address of N bits, so that it could be selectively called within 2^N different pagers.
The requirement was to support 65536 = 2^16 subscribers. This could be achieved by connecting 16 input pins to a logical 0 or 1. Other pins were needed: power 0V (logical 0), power +V (logical 1), input data signal, beeper output and reset input, so a total of 21 pins, for which a standard 24-pin package was needed. That was too big and too expensive. How could a much cheaper and smaller 16-pin package be used?
My solution was to use 8 pins each accepting two consecutive bits, requiring 4 extra output pins to provide these two bits, a total of 8 + 4 + 5 = 17, still 1 too many. One of the required 2 bit outputs could be avoided by inverting another externally, a practical solution.
Frontpage of the associated Dutct patent
3,919,652 Split Phase Signal Detector
Detector for a split-phase Manchester-dead binary signal.
This circuit just came to me and I was surprised that I was apparently the first to get a patent for it. Apparently there weren't many developers working on this yet.
3,952,250 Receiver for A Selective Pager System
It turned out that the digital part of the design for the above mentioned digital pager was also new. This was the part that was realized in LOCMOS. In doing so I continued on the idea of the bit synchronizer described in patent 3,716,780. In that the so-called integrate & dump principle was applied but I realized that the filter & sample was simpler here because it only had to be suitable for a single bit frequency.
3,980,825 System For The Transmission Of Split Phase Manchester Coded Bivalent Information Signals
In the digital pager mentioned above, not only a bit synchronizer was needed but also a frame synchronizer that ensured that the successive bits and bytes could be identified. The split-phase modulation used provided a very simple way to indicate where a new frame began.
With split-phase, each bit consists of two parts that are each other's inversion. This method was chosen because the signal is neutral on average. That makes it easy to determine the polarity of the input signal.
A new frame was indicated by having three successive half bits followed by three successive half bits with inverse polarity, whereby the signal still remains neutral on average. That also turned out to be worth a patent.
6,415,325 Transmission System With Improved Synchronisation
The previous patent was the last one I obtained during my hardware development period. After that I worked on software for microprocessor systems, where inventions were no longer protected by patents because they were copyrighted.
A few days before I left Philips Telecommunication Industries in May 1996, I filed another patent, which was not granted in the US until 2002.
It solved a problem in asynchronous data transmission systems, where transmission times are not precisely determined as in synchronous data transmission systems, and made it almost impossible to maintain synchronous clocks in ADT transmission systems.
In many cases, ADT obtains data from an SDT system. Both use frames with different but fixed lengths, so that the start of both frames coincides at regular intervals. Immediately after such a coincidence, ADT can insert the message "At the next coincidence it is time T". On the receiving end, this message is stored and used to set the local clock to T when the next coincidence occurs. The effect is that the transmission time of that message is accurately determined.
Even after I had filed this patent 15 years earlier, I was still asked for advice in 2011 to explain this patent!